In a DRAM memory system it is necessary to periodically refresh the contents of the storage cells in the memory. This is because information is held in the form of charge on a capacitor. The charge leaks off over time (it is volatile), and must therefore be read and rewritten to restore the original amount of charge.
As a consequence of the refresh requirement, memory controllers in DRAM systems periodically issue refresh commands that initiate refresh operations. Unfortunately, issuance of a refresh command prevents issuance of other commands (e.g., read and write) in a given time slot; moreover, read and write operations that might otherwise occur for selected memory banks are suspended during refresh operations directed to those banks. For both these reasons, the issuance of refresh commands reduces DRAM performance. The reduction in a DRAM system's performance due to refresh requirements is the system's “refresh overhead.”
One method used to reduce refresh overhead is to permit multiple banks (two or four, for example) to refresh a row simultaneously. This helps reduce the number of command slots needed to specify refresh commands, but aggravates the problem of bank contention because increasing the number of banks being refreshed increases the probability of a refresh operation conflicting with read or write operations. There is therefore a need for a way to reduce refresh overhead.